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VHDL STYDY NOTES-2

VHDL STUDY NOTES -1

1. Verilog Codes for Logic Gates in Structural Model

AND GATE:

 moduleandstr(x,y,z); 

inputx,y; 

output z;

and g1(z,x,y);

 endmodule 

NAND GATE:

 modulenandstr(x,y,z); 

inputx,y; 

output z;

 nand g1(z,x,y); 

endmodule

OR GATE

 module orstr(x,y,z);

 inputx,y;

 output z; 

or g1(z,x,y); 

endmodule 

NOR GATE

 modulenorstr(x,y,z);

 inputx,y; 

output z;

 nor g1(z,x,y);

 endmodule 

XNOR GATE

 module xorstr(x,y,z);

 inputx,y;

 output z; 

xor g1(z,x,y);

 endmodule 

NOT GATE

 modulexnorstr(x,y,z);

 inputx,y; 

output z;

 xnor g1(z,x,y); 

endmodule 

 module notstr(x,z);

 input x;

 output z;.

 not g1(z,x); 

endmodule

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